MC9328MX1_06 Datasheet, PDF (89/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Table 40. SSI (Port B Alternate Function) Timing Parameter Table
Ref
No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
Internal Clock Operation¹ (Port B Alternate Function²)
1 STCK/SRCK clock period¹
2 STCK high to STFS (bl) high³
3 SRCK high to SRFS (bl) high³
4 STCK high to STFS (bl) low³
5 SRCK high to SRFS (bl) low³
6 STCK high to STFS (wl) high³
7 SRCK high to SRFS (wl) high³
8 STCK high to STFS (wl) low³
9 SRCK high to SRFS (wl) low³
95
–
83.3
1.7
4.8
1.5
-0.1
1.0
-0.1
3.08
5.24
2.7
1.25
2.28
1.1
1.71
4.79
1.5
-0.1
1.0
-0.1
3.08
5.24
2.7
1.25
2.28
1.1
10 STCK high to STXD valid from high impedance
14.93
16.19
13.1
11a STCK high to STXD high
1.25
3.42
1.1
11b STCK high to STXD low
2.51
3.99
2.2
12 STCK high to STXD high impedance
12.43
14.59
10.9
13 SRXD setup time before SRCK low
20
–
17.5
14 SRXD hold time after SRCK low
0
–
0
External Clock Operation (Port B Alternate Function²)
15 STCK/SRCK clock period¹
92.8
–
81.4
16 STCK/SRCK clock high period
27.1
–
40.7
17 STCK/SRCK clock low period
18 STCK high to STFS (bl) high³
19 SRCK high to SRFS (bl) high³
20 STCK high to STFS (bl) low³
21 SRCK high to SRFS (bl) low³
22 STCK high to STFS (wl) high³
23 SRCK high to SRFS (wl) high³
24 STCK high to STFS (wl) low³
25 SRCK high to SRFS (wl) low³
61.1
–
40.7
–
92.8
0
–
92.8
0
–
92.8
0
–
92.8
0
–
92.8
0
–
92.8
0
–
92.8
0
–
92.8
0
26 STCK high to STXD valid from high impedance
18.9
29.07
16.6
27a STCK high to STXD high
9.23
20.75
8.1
27b STCK high to STXD low
10.60
21.32
9.3
–
ns
4.2
ns
1.0
ns
4.6
ns
2.0
ns
4.2
ns
1.0
ns
4.6
ns
2.0
ns
14.2
ns
3.0
ns
3.5
ns
12.8
ns
–
ns
–
ns
–
ns
–
ns
–
ns
81.4
ns
81.4
ns
81.4
ns
81.4
ns
81.4
ns
81.4
ns
81.4
ns
81.4
ns
25.5
ns
18.2
ns
18.7
ns
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
89