MC9328MX1_06 Datasheet, PDF (94/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
4.17.2 Non-Gated Clock Mode
Figure 70 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 71 shows the timing diagram
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in Table 43.
1
VSYNC
PIXCLK
6
4
5
DATA[7:0]
Valid Data
Valid Data
Valid Data
2
3
Figure 70. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
1
VSYNC
6
5
4
PIXCLK
DATA[7:0]
Valid Data
Valid Data
Valid Data
2
3
Figure 71. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
Table 43. Non-Gated Clock Mode Parameters
Ref No.
1
2
Parameter
csi_vsync to csi_pixclk
csi_d setup time
Min
Max
Unit
180
–
ns
1
–
ns
MC9328MX1 Technical Data, Rev. 7
94
Freescale Semiconductor