MC9328MX1_06 Datasheet, PDF (95/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Table 43. Non-Gated Clock Mode Parameters (Continued)
Ref No.
3
4
5
6
Parameter
csi_d hold time
csi_pixclk high time
csi_pixclk low time
csi_pixclk frequency
Min
Max
1
–
10.42
–
10.42
–
0
48
Unit
ns
ns
ns
MHz
The limitation on pixel clock rise time / fall time are not specified. It should be calculated from the hold
time and setup time, according to:
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore:
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
=> max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
=> max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
95