MC9328MX1_06 Datasheet, PDF (30/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Table 12. EIM Bus Timing Parameter Table (Continued)
Ref No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Min Typical Max Min Typical Max
4a Clock¹ rise to Output Enable Valid
2.32 2.62 6.85 2.3
2.6
6.8 ns
4b Clock¹ rise to Output Enable Invalid
2.11 2.52 6.55 2.1
2.5
6.5 ns
4c Clock¹ fall to Output Enable Valid
2.38 2.69 7.04 2.3
2.6
6.8 ns
4d Clock¹ fall to Output Enable Invalid
2.17 2.59 6.73 2.1
2.5
6.5 ns
5a Clock¹ rise to Enable Bytes Valid
1.91 2.52 5.54 1.9
2.5
5.5 ns
5b Clock¹ rise to Enable Bytes Invalid
1.81 2.42 5.24 1.8
2.4
5.2 ns
5c Clock¹ fall to Enable Bytes Valid
1.97 2.59 5.69 1.9
2.5
5.5 ns
5d Clock¹ fall to Enable Bytes Invalid
1.76 2.48 5.38 1.7
2.4
5.2 ns
6a Clock¹ fall to Load Burst Address Valid
2.07 2.79 6.73 2.0
2.7
6.5 ns
6b Clock¹ fall to Load Burst Address Invalid
1.97 2.79 6.83 1.9
2.7
6.6 ns
6c Clock¹ rise to Load Burst Address Invalid 1.91 2.62 6.45 1.9
2.6
6.4 ns
7a Clock¹ rise to Burst Clock rise
1.61 2.62 5.64 1.6
2.6
5.6 ns
7b Clock¹rise to Burst Clock fall
1.61 2.62 5.84 1.6
2.6
5.8 ns
7c Clock¹ fall to Burst Clock rise
1.55 2.48 5.59 1.5
2.4
5.4 ns
7d Clock¹ fall to Burst Clock fall
1.55 2.59 5.80 1.5
2.5
5.6 ns
8a Read Data setup time
5.54
–
– 5.5
–
–
ns
8b Read Data hold time
9a Clock¹ rise to Write Data Valid
9b Clock¹ fall to Write Data Invalid
9c Clock¹ rise to Write Data Invalid
0
–
–
0
–
1.81 2.72 6.85 1.8
2.7
1.45 2.48 5.69 1.4
2.4
1.63
–
– 1.62
–
–
ns
6.8 ns
5.5 ns
–
ns
10a DTACK setup time
2.52
–
– 2.5
–
–
ns
1 _{Clock refers to the system clock signal, HCLK, generated from the System DPLL}
4.4.1 DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 HCLK counts have elapsed. Only the CS5 group
supports DTACK signal function when the external DTACK signal is used for data acknowledgement.
4.4.2 DTACK Signal Timing
Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units
of measure for this figure are found in the associated tables.
MC9328MX1 Technical Data, Rev. 7
30
Freescale Semiconductor