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MC9328MX1_06 Datasheet, PDF (78/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors | |||
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Functional Description and Application Information
Table 32. PWM Output Timing Parameter Table (Continued)
Ref No.
Parameter
3b Clock rise time1
4a Output delay time1
4b Output setup time1
1 CL of PWMO = 30 pF
1.8 ± 0.1 V
Minimum
Maximum
â
6.67
5.7
â
5.7
â
3.0 ± 0.3 V
Unit
Minimum
Maximum
â
5/10
ns
5
â
ns
5
â
ns
4.13 SDRAM Controller
This section shows timing diagrams and parameters associated with the SDRAM (synchronous dynamic
random access memory) Controller.
1
SDCLK
CS
2
3S
3
3S
RAS
CAS
WE
3H
3S
3H
3H
3S
3H
ADDR
DQ
DQM
4S 4H
ROW/BA
COL/BA
8
3S
5
6
Data
7
3H
Note: CKE is high during the read/write cycle.
Figure 57. SDRAM Read Cycle Timing Diagram
MC9328MX1 Technical Data, Rev. 7
78
Freescale Semiconductor
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