MC9328MX1_06 Datasheet, PDF (79/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Table 33. SDRAM Read Timing Parameter Table
Ref
No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
1 SDRAM clock high-level width
2.67
–
4
2 SDRAM clock low-level width
6
–
4
3 SDRAM clock cycle time
11.4
–
10
3S CS, RAS, CAS, WE, DQM setup time
3.42
–
3
3H CS, RAS, CAS, WE, DQM hold time
2.28
–
2
4S Address setup time
3.42
–
3
4H Address hold time
2.28
–
2
5 SDRAM access time (CL = 3)
–
6.84
–
5 SDRAM access time (CL = 2)
–
6.84
–
5 SDRAM access time (CL = 1)
–
22
–
6 Data out hold time
2.85
–
2.5
7 Data out high-impedance time (CL = 3)
–
6.84
–
7 Data out high-impedance time (CL = 2)
–
6.84
–
7 Data out high-impedance time (CL = 1)
–
22
–
8 Active to read/write command period (RC = 1)
t_RCD1
–
t_RCD1
1 _{tRCD = SDRAM clock cycle time. This settings can be found in the MC9328MX1 reference manual.}
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
–
ns
6
ns
6
ns
22
ns
–
ns
6
ns
6
ns
22
ns
–
ns
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
79