MC9328MX1_06 Datasheet, PDF (87/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
SRCK Input
15
16
17
SRFS (bl) Input
19
21
23
25
SRFS (wl) Input
30
29
SRXD Input
Figure 67. SSI Receiver External Clock Timing Diagram
Table 39. SSI (Port C Primary Function) Timing Parameter Table
Ref No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
Internal Clock Operation¹ (Port C Primary Function²)
1
STCK/SRCK clock period¹
2
STCK high to STFS (bl) high³
3
SRCK high to SRFS (bl) high³
4
STCK high to STFS (bl) low³
5
SRCK high to SRFS (bl) low³
6
STCK high to STFS (wl) high³
7
SRCK high to SRFS (wl) high³
8
STCK high to STFS (wl) low³
9
SRCK high to SRFS (wl) low³
95
–
83.3
1.5
4.5
1.3
-1.2
-1.7
-1.1
2.5
4.3
2.2
0.1
-0.8
0.1
1.48
4.45
1.3
-1.1
-1.5
-1.1
2.51
4.33
2.2
0.1
-0.8
0.1
10 STCK high to STXD valid from high impedance
14.25
15.73
12.5
11a STCK high to STXD high
0.91
3.08
0.8
11b STCK high to STXD low
0.57
3.19
0.5
12 STCK high to STXD high impedance
12.88
13.57
11.3
13 SRXD setup time before SRCK low
21.1
–
18.5
14 SRXD hold time after SRCK low
0
–
0
External Clock Operation (Port C Primary Function²)
15 STCK/SRCK clock period¹
92.8
–
81.4
16 STCK/SRCK clock high period
27.1
–
40.7
17 STCK/SRCK clock low period
61.1
–
40.7
–
ns
3.9
ns
-1.5
ns
3.8
ns
-0.8
ns
3.9
ns
-1.5
ns
3.8
ns
-0.8
ns
13.8
ns
2.7
ns
2.8
ns
11.9
ns
–
ns
–
ns
–
ns
–
ns
–
ns
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
87