MC9328MX1_06 Datasheet, PDF (92/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
2 _{There is one set of I/O signals for the SSI2 module. They are from Port C alternate function (PC19 – PC24). When SSI signals}
are configured as outputs, they can be viewed at Port C alternate function a. When SSI signals are configured as inputs, the
SSI module selects the input based on FMCR register bits in the Clock controller module (CRM). By default, the input is selected
from Port C alternate function.
3 _{bl = bit length; wl = word length}
4.17 CMOS Sensor Interface
The CMOS Sensor Interface (CSI) module consists of a control register to configure the interface timing,
a control register for statistic data generation, a status register, interface logic, a 32 × 32 image data receive
FIFO, and a 16 × 32 statistic data FIFO.
4.17.1 Gated Clock Mode
Figure 68 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 69 shows the timing diagram
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in Table 42.
1
VSYNC
7
HSYNC
PIXCLK
5
6
2
DATA[7:0]
Valid Data
Valid Data
Valid Data
3
4
Figure 68. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
MC9328MX1 Technical Data, Rev. 7
92
Freescale Semiconductor