MC9328MX1_06 Datasheet, PDF (27/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Parameter
Phase jitter (p-p)
Power supply voltage
Power dissipation
Functional Description and Application Information
Table 10. DPLL Specifications (Continued)
Test Conditions
Integer MF, FPL mode, Vcc=1.8V
–
FOL mode, integer MF,
f_dck = MHz, Vcc = 1.8V
Minimum Typical Maximum Unit
–
1.0
(10%)
1.5
ns
1.7
–
2.5
V
–
–
4
mW
4.3 Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and
Figure 4.
NOTE
Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up
to prevent forward biasing.
90% AVDD
1
POR
RESET_POR
RESET_DRAM
HRESET
RESET_OUT
CLK32
10% AVDD
2
Exact 300ms
3
7 cycles @ CLK32
4
14 cycles @ CLK32
HCLK
Figure 3. Timing Relationship with POR
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
27