MC9328MX1_06 Datasheet, PDF (88/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Table 39. SSI (Port C Primary Function) Timing Parameter Table (Continued)
Ref No.
Parameter
18 STCK high to STFS (bl) high³
19 SRCK high to SRFS (bl) high³
20 STCK high to STFS (bl) low³
21 SRCK high to SRFS (bl) low³
22 STCK high to STFS (wl) high³
23 SRCK high to SRFS (wl) high³
24 STCK high to STFS (wl) low³
25 SRCK high to SRFS (wl) low³
26 STCK high to STXD valid from high impedance
27a STCK high to STXD high
27b STCK high to STXD low
28 STCK high to STXD high impedance
29 SRXD setup time before SRCK low
30 SRXD hole time after SRCK low
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
–
92.8
0
–
92.8
0
–
92.8
0
–
92.8
0
–
92.8
0
–
92.8
0
–
92.8
0
–
92.8
0
18.01
28.16
15.8
8.98
18.13
7.0
9.12
18.24
8.0
18.47
28.5
16.2
1.14
–
1.0
0
–
0
81.4
ns
81.4
ns
81.4
ns
81.4
ns
81.4
ns
81.4
ns
81.4
ns
81.4
ns
24.7
ns
15.9
ns
16.0
ns
25.0
ns
–
ns
–
ns
Synchronous Internal Clock Operation (Port C Primary Function²)
31 SRXD setup before STCK falling
32 SRXD hold after STCK falling
15.4
–
13.5
–
ns
0
–
0
–
ns
Synchronous External Clock Operation (Port C Primary Function²)
33 SRXD setup before STCK falling
1.14
–
1.0
–
ns
34 SRXD hold after STCK falling
0
–
0
–
ns
1 _{All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync}
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
2 _{There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B}
alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary
function and Port B alternate function. When SSI signals are configured as input, the SSI module selects the input based on
status of the FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary
function.
3 _{bl = bit length; wl = word length.}
MC9328MX1 Technical Data, Rev. 7
88
Freescale Semiconductor