MC9328MX1_06 Datasheet, PDF (28/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
5
RESET_IN
HRESET
RESET_OUT
6
CLK32
14 cycles @ CLK32
4
HCLK
Figure 4. Timing Relationship with RESET_IN
Table 11. Reset Module Timing Parameter Table
Ref
No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Min
Max
Min Max
1 Width of input POWER_ON_RESET
note¹
–
note¹
–
–
2 Width of internal POWER_ON_RESET
(9600 *CLK32 at 32 kHz)
300
300
300 300
ms
3 7K to 32K-cycle stretcher for SDRAM reset
7
7
7
7
Cycles of
CLK32
4 14K to 32K-cycle stretcher for internal system reset
14
14
14
14
Cycles of
HRESERT and output reset at pin RESET_OUT
CLK32
5 Width of external hard-reset RESET_IN
4
–
4
–
Cycles of
CLK32
6 4K to 32K-cycle qualifier
4
4
4
4
Cycles of
CLK32
1 _{POR width is dependent on the 32 or 32.768 kHz crystal oscillator start-up time. Design margin should allow for crystal}
tolerance, i.MX chip variations, temperature impact, and supply voltage influence. Through the process of supplying crystals
for use with CMOS oscillators, crystal manufacturers have developed a working knowledge of start-up time of their crystals.
Typically, start-up times range from 400 ms to 1.2 seconds for this type of crystal.
If an external stable clock source (already running) is used instead of a crystal, the width of POR should be ignored in
calculating timing for the start-up process.
4.4 External Interface Module
The External Interface Module (EIM) handles the interface to devices external to the i.MX1 processor,
including the generation of chip-selects for external peripherals and memory. The timing diagram for the
EIM is shown in Figure 5, and Table 12 defines the parameters of signals.
MC9328MX1 Technical Data, Rev. 7
28
Freescale Semiconductor