MC9328MX1_06 Datasheet, PDF (75/100 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
CMD
******
P S T CMD52 CRC E Z Z Z
******
DAT[1] _{S Block Data E Z Z L H}
For 4-bit
S Block Data E
DAT[2] _{S Block Data E Z Z L L L L L L L L L L L L L L L L L L L L L H Z S Block Data E}
For 4-bit
Figure 54. SDIO ReadWait Timing Diagram
4.11 Memory Stick Host Controller
The Memory Stick protocol requires three interface signal line connections for data transfers: MS_BS,
MS_SDIO, and MS_SCLKO. Communication is always initiated by the MSHC and operates the bus in
either four-state or two-state access mode.
The MS_BS signal classifies data on the SDIO into one of four states (BS0, BS1, BS2, or BS3) according
to its attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet
transmissions occur. During the BS1, BS2, and BS3 states, packet communications are executed. The BS1,
BS2, and BS3 states are regarded as one packet length and one communication transfer is always
completed within one packet length (in four-state access mode).
The Memory Stick usually operates in four state access mode and in BS1, BS2, and BS3 bus states. When
an error occurs during packet communication, the mode is shifted to two-state access mode, and the BS0
and BS1 bus states are automatically repeated to avoid a bus collision on the SDIO.
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
75