MC68HC705CT4 Datasheet, PDF (91/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Dual Phase-Locked Loop (PLL)
Registers
11.3.4 16-Bit Receive Counter Modulus Register
This 2-byte register holds the count for the 16-bit receive counter. The
receive counter is shut off and held in reset when the RXON bit is
cleared. For proper operation, this register must not be loaded with a
value less than $000F.
Address: $000F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PLLRX15 PLLRX14 PLLRX13 PLLRX12 PLLRX11 PLLRX10 PLLRX9 PLLRX8
Write:
Reset: 0
0
0
0
0
0
0
0
Address: $0010
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PLLRX7 PLLRX6 PLLRX5 PLLRX4 PLLRX3 PLLRX2 PLLRX1 PLLRX0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 11-5. 16-Bit Receive Counter (PLLRX)
The modulus registers mentioned above have specific read/write logic.
When the user updates the contents of the modulus registers, the MSB
must be written first and is temporarily stored in a temporary buffer. This
inhibits the transfer of data from this level to the next level, which is the
modulus register. When the LSB is written, all 12 or 16 bits (data from
the temporary buffer and the MCU internal bus) are transferred to the
modulus register simultaneously. This prevents the loading of bad data
from the modulus register. A read of the data registers is the reverse of
a write operation. A read of the LSB buffers the MSB. A subsequent read
of the MSB reflects this buffered value. Since only one temporary buffer
exists, two sequential MSB writes of different registers will result in only
the last data value stored in the temporary buffer. The first value will be
lost.
MC68HC705CT4 — Rev. 2.0
MOTOROLA
General Release Specification
Dual Phase-Locked Loop (PLL)
91
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