MC68HC705CT4 Datasheet, PDF (40/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Interrupts
Freescale Semiconductor, Inc.
When edge and level sensitivity is selected for the IRQ interrupt, it is
sensitive to the following cases:
• Low level on the IRQ pin
• Falling edge on the IRQ pin
• Falling edge or low level on any port C pin with keyscan enabled
4.8 External Interrupt Timing
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts
(internal and external) are disabled. Clearing the I bit enables interrupts.
The interrupt request is latched immediately following the falling edge of
the IRQ source. The interrupt request is then synchronized internally and
serviced as specified by the contents of $1FFA and $1FFB.
Either a level-sensitive and edge-sensitive trigger or an edge-sensitive-
only trigger is available via the mask programmable option for the IRQ
pin.
4.9 16-Bit Timer Interrupt
Three different timer interrupt flags cause a timer interrupt whenever
they are set and enabled. The interrupt flags are in the timer status
register (TSR), and the enable bits are in the timer control register
(TCR). Any of these interrupts vector to the same interrupt service
routine, located at the address specified by the contents of memory
locations $1FF8 and $1FF9.
4.10 SSI Interrupt
Two different synchronous serial interrupt (SSI) flags cause an SSI
interrupt whenever they are set and enabled. The interrupt flags are in
the SSI status register (SSSR), and the enable bits are in the SSI control
register (SSCR). Either of these interrupts vector to the same interrupt
service routine, located at the address specified by the contents of
memory locations $1FF6 and $1FF7.
General Release Specification
MC68HC705CT4 — Rev. 2.0
40
Interrupts
MOTOROLA
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