MC68HC705CT4 Datasheet, PDF (61/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
16-Bit Timer
Counter Register
INTERNAL BUS
HIGH LOW
BYTE BYTE
INTERNAL
PROCESSOR
CLOCK
8-BIT
BUFFER
$16 OUTPUT
$17
COMPARE
REGISTER
÷4
HIGH
BYTE
LOW
BYTE
16-BIT FREE _$18
RUNNING
COUNTER $19
COUNTER ^$1A
ALTERNATE
REGISTER
$1B
HIGH LOW
BYTE BYTE
INPUT ^$14
CAPTURE
REGISTER ^$15
OUTPUT
COMPARE
CIRCUIT
OVERFLOW
DETECT
CIRCUIT
EDGE
DETECT
CIRCUIT
DQ
TIMER
STATUS ICF OCF TOF $13
REG.
CLK
OUTPUT
LEVEL C
REG.
TIMER ^RESET
FOLVL ICIE OCIE TOIE IEDG OLVL CONTROL
REG.
$12
INTERRUPT CIRCUIT
OUTPUT
LEVEL
(TCMP)
PD6
EDGE
INPUT
(TCAP)
Figure 8-1. 16-Bit Timer Block Diagram
The free-running counter is configured to $FFFC during reset and is a
read-only register but only when the timer is enabled. During a power-on
reset, the counter is also preset to $FFFC and begins running only after
the TON bit in the TIMER control register is set. Because the free-
running counter is 16 bits preceded by a fixed divided-by-four prescaler,
the value in the free-running counter repeats every 262,144 internal bus
clock cycles. When the counter rolls over from $FFFF to $0000, the TOF
bit is set. An interrupt can also be enabled when counter roll-over occurs
by setting its interrupt enable bit (TOIE).
NOTE:
The I bit in the CCR should be set while manipulating both the high and
low byte registers of a specific timer function to ensure that an interrupt
does not occur.
MC68HC705CT4 — Rev. 2.0
MOTOROLA
General Release Specification
16-Bit Timer
61
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