MC68HC705CT4 Datasheet, PDF (64/152 Pages) Freescale Semiconductor, Inc – General Release Specification

16-Bit Timer
Freescale Semiconductor, Inc.
8.6 Timer Control Register
The TCR is a read/write register containing six control bits. Three bits
control interrupts associated with the timer status register flags ICF,
OCF, and TOF.
Address: $0012
Bit 7
6
5
4
Read:
ICIE OCIE TOIE
0
Write:
Reset: 0
0
0
0
3
2
1
Bit 0
0
TON IEDG OLVL
0
0
0
0
Figure 8-2. Timer Control Register (TCR)
ICIE — Input Capture Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
OCIE — Output Compare Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
TOIE — Timer Overflow Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
TON — Timer On
When disabled, the timer is initialized to the reset condition.
1 = Timer enabled
0 = Timer disabled
IEDG — Input Edge
Value of input edge determines which level transition on the TCAP pin
will trigger a free-running counter transfer to the input capture
register. Reset clears this bit.
1 = Positive edge
0 = Negative edge
General Release Specification
MC68HC705CT4 — Rev. 2.0
64
16-Bit Timer
MOTOROLA
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