MC68HC705CT4 Datasheet, PDF (84/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Core Timer
Freescale Semiconductor, Inc.
10.5 Computer Operating Properly (COP) Reset
The COP watchdog timer function is implemented on this device by
using the output of the RTI circuit and further dividing it by eight. The
minimum COP reset rates are listed in Table 10-2. If the COP circuit
times out, an internal reset is generated and the normal reset vector is
fetched. Preventing a COP timeout or clearing the COP is accomplished
by writing a logic 0 to bit 0 of address $1FF0. When the COP is cleared,
only the final divide-by-eight stage (output of the RTI) is cleared.
If the COP watchdog timer is allowed to time out, an internal reset is
generated to reset the MCU. In addition, the RESET pin is pulled low for
a minimum of one E-clock cycle for emulation purposes.
The COP remains enabled after execution of the WAIT instruction and
all associated operations apply. If the STOP instruction is disabled,
execution of STOP instruction causes the CPU to execute a NOP
instruction. In addition, the COP is prohibited from being held in RESET.
This prevents a device lock-up condition.
This COP’s objective is to make it impossible for this device to become
stuck or locked-up and to be sure the COP is able to rescue the part from
any situation where it might entrap itself in abnormal or unintended
behavior. This function is a mask option.
10.6 Timer During Wait Mode
The CPU clock halts during wait mode, but the timer remains active. If
interrupts are enabled, a timer interrupt will cause the processor to exit
wait mode. The COP is always enabled while in user mode.
10.7 Core Timer Power Supply Source
The core timer is supplied by V_DD and V_SS. V_DD2 and V_SS2 are not
needed here because this module is not susceptible to supply noise.
General Release Specification
MC68HC705CT4 — Rev. 2.0
84
Core Timer
MOTOROLA
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