MC68HC705CT4 Datasheet, PDF (65/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
16-Bit Timer
Timer Status Register
OLVL — Output Level
Value of output level is clocked into the output level register by the
next successful output compare and will appear on the TCMP pin.
1 = High output
0 = Low output
8.7 Timer Status Register
The TSR is a read-only register containing three status flag bits.
Address: $0013
Bit 7
6
5
4
3
2
1
Bit 0
Read: ICF
OCF
TOF
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-3. Timer Status Register (TSR)
ICF — Input Capture Flag
1 = Flag set when selected polarity edge is sensed by input capture
edge detector
0 = Flag cleared when TSR and input capture low register ($15) are
accessed
Reset clears this bit.
OCF — Output Compare Flag
1 = Flag set when output compare register contents match the free-
running counter contents
0 = Flag cleared when TSR and output compare low register ($17)
are accessed
Reset clears this bit.
MC68HC705CT4 — Rev. 2.0
MOTOROLA
General Release Specification
16-Bit Timer
65
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