MC68HC705CT4 Datasheet, PDF (76/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Synchronous Serial Interface (SSI)
9.4.3 SSI Data Register
This register is located at address $001D and is both the transmit and
receive data register. This system is not double buffered, but any writes
to this register during transfers are masked and will not destroy the
previous contents. The SDR can be read at any time, but, if a transfer is
in progress the results may be ambiguous. The contents of this register
could be altered whenever the CPOL bit is altered. This register should
be written to only upon completion of a transfer, after the SF flag has
been cleared. Otherwise, the new data will not be stored.
For an SSI configured as a master, to initiate a transfer, the data register
write must occur after the SSI is enabled.
Address: $001D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset: U
U
U
U
U
U
U
U
Figure 9-5. SSI Data Register (SDR)
9.5 Operation During Wait Mode
The CPU clock halts during wait mode, but the SSI remains active. If
interrupts are enabled, an SSI interrupt will cause the processor to exit
wait mode.
9.6 Operation During Stop Mode
In stop mode, the SSI halts operation. The SDIO and SCK pins will
maintain their states.
If the SSI is nearing completion of a transfer when the stop mode is
entered, it might be possible for the SSI to generate an interrupt request
and thus cause the processor immediately to exit stop mode. To prevent
General Release Specification
MC68HC705CT4 — Rev. 2.0
76
Synchronous Serial Interface (SSI)
MOTOROLA
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