MC68HC705CT4 Datasheet, PDF (39/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Interrupts
Hardware Interrupts
4.6 Hardware Interrupts
All hardware interrupts except RESET are maskable by the I bit in the
CCR. If the I bit is set, all hardware interrupts (internal and external) are
disabled. Clearing the I bit enables the hardware interrupts. The two
types of hardware interrupts are explained in the following sections.
4.7 External Interrupt (IRQ)
The IRQ pin provides an asynchronous interrupt to the CPU. A block
diagram of the IRQ function is shown in Figure 4-2.
NOTE:
The BIH and BIL instructions will apply only to the level on the IRQ pin
itself, and not to the output of the logic OR function with the port C IRQ
interrupts. The state of the individual port C pins can be checked by
reading the appropriate port C pins as inputs.
IRQ PIN
V_DD
PORT C
IRQ VECTOR FETCH
RST
LEVEL
(MASK OPTION)
IRQ
LATCH
R
Figure 4-2. IRQ Function Block Diagram
TO BIH & BIL
INSTRUCTION
SENSING
TO IRQ
PROCESSING
IN CPU
The IRQ pin is one source of an external interrupt. All port C pins
(PC0–PC7) act as other external interrupt sources if the keyscan feature
is enabled as specified by the user.
When edge sensitivity is selected for the IRQ interrupt, it is sensitive to:
• Falling edge on the IRQ pin
• Falling edge on any port C pin with keyscan enabled
MC68HC705CT4 — Rev. 2.0
MOTOROLA
General Release Specification
Interrupts
39
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