MC68HC705CT4 Datasheet, PDF (57/152 Pages) Freescale Semiconductor, Inc – General Release Specification

7.6 Port D
Freescale Semiconductor, Inc.
Parallel Input/Output (I/O)
Port D
Port D is a 7-bit bidirectional port. Two of its pins are shared with the SSI
subsystem, four are shared with the comparators, and one is shared with
the timer. During reset, all seven bits become valid input ports because
all special function output drivers associated with the timer and SSI
subsystems are disabled.
7.7 Input/Output Port Pin Programming
Port pins may be programmed as inputs or outputs under software
control. The direction of the pins is determined by the state of the
corresponding bit in the port data direction register (DDR). Each I/O port
has an associated DDR. Any I/O port pin is configured as an output if its
corresponding DDR bit is set to a logic one. A pin is configured as an
input if its corresponding DDR bit is cleared to a logic 0.
At power-on or reset, all DDRs are cleared, which configures all pins as
inputs. The data direction registers are capable of being written to or
read by the processor. During the programmed output state, a read of
the data register actually reads the value of the output data latch and not
the I/O pin.
Refer to Table 7-1 and to Figure 7-2 for additional information.
Table 7-1. I/O PIn Functions
R/W
DDR
I/O Pin Functions
0
0
The I/O pin is in input mode. Data is written into the output
data latch.
0
1
Data is written into the output data latch and output to the
I/O pin.
1
0
The state of the I/O pin is read.
1
1
The I/O pin is in an output mode. The output data latch is
read.
MC68HC705CT4 — Rev. 2.0
MOTOROLA
General Release Specification
Parallel Input/Output (I/O)
57
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