MC68HC705CT4 Datasheet, PDF (74/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Synchronous Serial Interface (SSI)
When cleared, this bit configures the SSI to the slave mode and
aborts any transmission in progress. Transfers are initiated by an
external master, which should supply the clock to the SCK pin.
CPOL — Clock Polarity
The clock polarity bit controls the state of the SCK pin between
transmissions.
When this bit is set, pin SCK is high between transmissions.
When this bit is cleared, pin SCK is low between transmissions.
In both cases the data is latched on the rising edge of SCK for serial
input and is valid on the rising edge of SCK for serial output. A reset
sets this bit.
NOTE:
If the SSI is used as a slave, the SCK input pin must be active before
enabling the SSI. For example, if CPOL = 0, SCK must be low; if
CPOL = 1, SCK must be high.
T/R — Transmit/Receive
This bit must be set to allow data to be driven on the SDIO pin
(transmitting). It must be cleared to disable the SDIO drivers when
receiving data. It is cleared by a reset.
SR1 and SR0 — SSI Rate
These bits determine the frequency of SCK when in master mode
(MSTR = 1). They have no effect in slave mode (MSTR = 0).
Table 9-1. SSI Rates
SR1 and SR0
00
01
10
11
SCK Rates (Hz) at f_osc Frequency
32 kHz
64 kHz
128 kHz
256 kHz
General Release Specification
MC68HC705CT4 — Rev. 2.0
74
Synchronous Serial Interface (SSI)
MOTOROLA
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