MC68HC705CT4 Datasheet, PDF (72/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Synchronous Serial Interface (SSI)
If (CPOL = 0), the first data bit will be driven out to the SDIO pin before
the first rising edge of SCK. Subsequent falling edges of SCK will shift
the remaining data bits out.
When receiving data in master mode, the T/R bit must be low and data
must be written to the data register to initiate clock generation.
When transmitting data in master mode, the T/R bit must be high.
When receiving data in slave mode, T/R bit must be low and the clock
and data must be supplied by external device.
When transmitting data in slave mode, T/R bit must be high, and data
must be written to the data register before the SSI is enabled to ensure
that proper data is transferred.
SCK
(CPOL = 1)
SDIO
SCK
(CPOL = 0)
SE
BIT 1
BIT 2
BIT 3
BIT 7
BIT 8
Figure 9-2. Serial I/O Port Timing
9.4 SSI Registers
The SSI has three registers: control, status, and data.
9.4.1 SSI Control Register
This register is located at address $001E and contains seven bits. A
reset clears all of these bits, except bit 3 which is set. Writes to this
register during a transfer should be avoided, with the exception of
clearing the SE bit to disable the SSI.
In addition, the clock polarity, rate, data format and master/slave
selection should not be changed while the SSI is enabled (SE = 1) or
General Release Specification
MC68HC705CT4 — Rev. 2.0
72
Synchronous Serial Interface (SSI)
MOTOROLA
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