MC68HC705CT4 Datasheet, PDF (87/152 Pages) Freescale Semiconductor, Inc – General Release Specification

11.3 Registers
Freescale Semiconductor, Inc.
Dual Phase-Locked Loop (PLL)
Registers
The PLL has one 12-bit programmable counter, two 16-bit
programmable counters, and one control register.
11.3.1 Dual Control Register
The PLLCR contains bits that affect the operation of the PLL.
Address: $000A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
TLOCK RLOCK
REFON TXON RXON
PLS1
PLS0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-2. Dual PLL Control Register
PLS1 and PLS0 — PLL Reference Counter Select
These bits select between the PLL reference counter MUX outputs.
This output signal then drives the phase detectors.
Table 11-1. PLL Reference Counter Select
PLS1 and PLS0 PLL Reference Counter Output
00
÷12-Bit Counter
01
÷4 After 12-Bit Counter
10
÷5 After 12-Bit Counter
11
÷25 After 12-Bit Counter
RXON — RX Counter Enable
When set, this bit enables the PLL receive counter.
When clear, it stops the receive counter in a reset state to save power.
RXON also shuts off the associated phase detector and holds it in
three-state. Initializing the receive counter before it is enabled is
recommended.
MC68HC705CT4 — Rev. 2.0
MOTOROLA
General Release Specification
Dual Phase-Locked Loop (PLL)
87
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