MC68HC705CT4 Datasheet, PDF (83/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Core Timer
Core Timer Counter Register
10.4 Core Timer Counter Register
The timer counter register is a read-only register that contains the
current value of the 8-bit ripple counter at the beginning of the timer
chain. This counter is clocked by the CPU clock (E/4) and can be used
for various functions including a software input capture. Extended time
periods can be attained using the TOF function to increment a temporary
RAM storage location, thereby simulating a 16-bit (or more) counter.
Address $0009
Bit 7
6
5
4
3
2
1
Bit 0
Read: D7
D6
D5
D4
D3
D2
D1
D0
Write:
Reset: 0
0
0
0
0
0
1
1
= Unimplemented
Figure 10-3. Core Counter Register (CTCR)
The power-on cycle clears the entire counter chain and begins clocking
the counter. After 4064 cycles, the power-on reset circuit is released,
which again clears the counter chain and allows the device to come out
of reset. At this point, if RESET is not asserted, the timer starts counting
up from zero and normal device operation begins. When RESET is
asserted any time during operation (other than POR), the counter chain
is cleared.
MC68HC705CT4 — Rev. 2.0
MOTOROLA
General Release Specification
Core Timer
83
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