MC68HC705CT4 Datasheet, PDF (48/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Resets
Freescale Semiconductor, Inc.
Table 5-1. COP Watchdog Timer Recommendations
IF the following conditions exist:
WAIT Time
WAIT Time less than COP Timeout
WAIT Time More than COP Timeout
Any length WAIT Time
THEN the COP Watchdog Timer should be:
Enable or Disable COP by Mask Option
Disable COP by Mask Option
Disable COP by Mask Option
5.4.2.5 COP Register
The COP register is shared with the MSB of an unimplemented user
interrupt vector as shown in Figure 5-3. Reading this location returns
whatever user data has been programmed at this location. Writing a zero
to the COPR bit in this location clears the COP watchdog timer.
Addr
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$1FF0
Unimplemented Vector ^{Read: X}
and COP Watchdog Timer _Write:
X
X
X
X
X
X
X
COPR
= Unimplemented
Figure 5-3. COP Watchdog Timer Location
5.4.3 Illegal Address
An illegal address reset is generated when the CPU attempts to fetch an
instruction from either unimplemented address space ($0130 to $0AFF)
or I/O address space ($0000 to $002F).
General Release Specification
MC68HC705CT4 — Rev. 2.0
48
Resets
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com