MC68HC705CT4 Datasheet, PDF (89/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Dual Phase-Locked Loop (PLL)
Registers
11.3.2 12-Bit Reference Counter Modulus Register
This 2-byte register holds the count for the 12-bit reference counter. The
reference counter is shut off and held in reset when the REFON bit is
cleared. For proper operation, this register must not be loaded with a
value less than $000F.
Address: $000B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
PLLRC11 PLLRC10 PLLRC9 PLLRC8
Reset: 0
0
0
0
0
0
0
0
Address: $000C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PLLRC7 PLLRC6 PLLRC5 PLLRC4 PLLRC3 PLLRC2 PLLRC1 PLLRC0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-3. 12-Bit Reference Counter (PLLRC)
NOTE: Bit 4 to bit 7 of $000B are not used but they are physically present. The
user may use these four bits for scratch memory.
MC68HC705CT4 — Rev. 2.0
MOTOROLA
General Release Specification
Dual Phase-Locked Loop (PLL)
89
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