MC68HC705CT4 Datasheet, PDF (86/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Dual Phase-Locked Loop (PLL)
11.2 Introduction
This dual PLL is similar to that of the MC145162 60-MHz universal
programmable dual PLL frequency synthesizer. It is especially designed
for CT-1 cordless phone applications.
The PLL features fully programmable 16-bit receive, 16-bit transmit, and
12-bit reference ripple down counters. It also has two independent
phase detectors for transmit and receive loops.
The FinTx and FinRx signals are input to the PLL transmit and receive
counters, respectively. They are typically driven by the loop VCO and
AC-coupled. The minimum input signal level is 200 mV_p-p @ 60.0 MHz.
OSC
(10.24 MHz)
12-BIT PROGRAMMABLE
REFERENCE COUNTER
MCU BUS
÷4
÷ 25
÷5
PLS1
PLS0
FinT
16-BIT PROGRAMMABLE
TX COUNTER
TX
PHASE
DETECTOR
TxPDOUT
RX
PHASE
DETECTOR
RxPDOUT
FinR
16-BIT PROGRAMMABLE
RX COUNTER
Figure 11-1. Dual PLL Block Diagram
General Release Specification
MC68HC705CT4 — Rev. 2.0
86
Dual Phase-Locked Loop (PLL)
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com