MC68HC705CT4 Datasheet, PDF (47/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Resets
Internal Resets
of address $1FF0. A read of address $1FF0 returns user data
programmed at that location.
5.4.2.2 COP During Wait Mode
The COP continues to operate normally during wait mode. The software
should pull the device out of wait mode periodically and reset the COP
by writing to the COPF bit to prevent a COP reset.
5.4.2.3 COP During Stop Mode
When the stop enable mask option is selected, stop mode disables the
oscillator circuit and thereby turns the clock off for the entire device.
When STOP is executed, the COP counter will hold its current state. If a
reset is used to exit stop mode, the COP counter is reset and held until
4064 POR cycles are completed, at that time, counting will begin. If an
external IRQ is used to exit stop mode, the COP counter does not wait
for the completion of the 4064 POR cycles but it does count these
cycles. It is recommended, therefore, that the COP is fed before
executing the STOP instruction.
5.4.2.4 COP Watchdog Timer Considerations
The COP watchdog timer is active in all modes of operation if enabled
by a mask option. If the COP watchdog timer is selected by a mask
option, any execution of the STOP instruction (either intentional or
inadvertent due to the CPU being disturbed) causes the oscillator to halt
and prevent the COP watchdog timer from timing out. If the COP
watchdog timer is selected by a mask option, the COP resets the MCU
when it times out. Therefore, it is recommended that the COP watchdog
is disabled for a system that must have intentional uses of the wait
mode for periods longer than the COP timeout period.
The recommended interactions and considerations for the COP
watchdog timer, STOP instruction, and WAIT instruction are
summarized in Table 5-1.
MC68HC705CT4 — Rev. 2.0
MOTOROLA
General Release Specification
Resets
47
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