MC68HC705CT4 Datasheet, PDF (53/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Operating Modes
Low-Power Modes
During wait mode, the I bit in the CCR is cleared to enable interrupts. All
other registers, memory, and input/output lines remain in their previous
state. The timer may be enabled to allow a periodic exit from wait mode.
6.5.4 Low-Power Wait
When the wait mode is entered by executing the WAIT instruction, the
oscillator divider changes from a divide-by-5 to a divide-by-40 (additional
divide-by-8) to lower the wait current. As a result, this gives a CPU clock
rate of 256 kHz if the oscillator is running with a 10.24-MHz crystal. The
oscillator divide-by-5 or divide-by-40 option is also controlled by the
speed bit located in the miscellaneous control register ($21).
Section 14. Miscellaneous Register. When returning from wait mode
via an interrupt, the OSC rate prior to entering wait mode is restored.
MC68HC705CT4 — Rev. 2.0
MOTOROLA
General Release Specification
Operating Modes
53
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