MC68HC705CT4 Datasheet, PDF (70/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Synchronous Serial Interface (SSI)
Transmission in master mode is initiated by a write to the SSI data
register (SDR). A transfer cannot be initiated in slave mode; the external
master initiates the transfer. The programmer must choose between
master or slave mode before the SSI is enabled. The programmer must
ensure that only one master exists in the system at any one time. All
devices in the system must operate with the same clock polarity and
data rates. Slaves should always be disabled before the master is
disabled.
MCU INTERNAL BUS
CONTROLS/ADDRESS BUS
DATA BUS
CONTROL LOGIC
000000
SSI STATUS REG.
SSI CONTROL REG.
CLOCK GENERATOR
SSI DATA REG.
LSBF
SE
&
MSTR
Figure 9-1. SSI Block Diagram
INTERRUPT CIRCUIT
TO INTERRUPT LOGIC
HFF
SDIO
SCK
General Release Specification
MC68HC705CT4 — Rev. 2.0
70
Synchronous Serial Interface (SSI)
MOTOROLA
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