MC68HC705CT4 Datasheet, PDF (46/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Resets
Freescale Semiconductor, Inc.
5.4 Internal Resets
The three internally generated resets are the initial power-on reset
function, the COP watchdog timer reset, and the illegal address detector.
Termination of the external RESET input or the internal COP watchdog
timer are the only reset sources that can alter the operating mode of the
MCU. The other internal resets do not have any effect on the mode of
operation when their reset state ends.
5.4.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and is not
able to detect a drop in the power supply voltage (brown-out). There is
an oscillator stabilization delay of 4064 internal processor bus clock
cycles (PH2) after the oscillator becomes active.
The POR generates the RST signal that resets the CPU. If any other
reset function is active at the end of this 4064-cycle delay, the RST
signal remains in the reset condition until the other reset condition(s)
end. During the POR, the RESET pin is forced low.
5.4.2 Computer Operating Properly Reset (COPR)
The MCU contains a watchdog timer that automatically times out if not
reset (cleared) within a specific time by a program reset sequence. If the
COP watchdog timer is allowed to time out, an internal reset is
generated to reset the MCU. Regardless of an internal or external
RESET, the MCU comes out of a COP reset according to the standard
rules of mode selection.
The COP reset function is enabled or disabled by a mask option and is
verified during production testing.
5.4.2.1 Resetting the COP
Writing a zero to the COPF bit prevents a COP reset. This action resets
the counter and begins the timeout period again. The COPF bit is bit 0
General Release Specification
MC68HC705CT4 — Rev. 2.0
46
Resets
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