MC68HC705CT4 Datasheet, PDF (82/152 Pages) Freescale Semiconductor, Inc – General Release Specification

Core Timer
Freescale Semiconductor, Inc.
TOFC — Timer Overflow Flag Clear
When a logic 1 is written to this bit, CTOF is cleared. Writing a logic 0
has no effect on the CTOF bit. This bit always reads as zero.
RTFC — Real-Time Interrupt Flag Clear
When a logic 1 is written to this bit, RTIF is cleared. Writing a logic 0
has no effect on the RTIF bit. This bit always reads as zero.
RT1 and RT0 — Real-Time Interrupt Rate Select
These two bits select one of four taps from the real-time interrupt
circuit. See Table 10-2. Reset sets these two bits, which selects the
slowest periodic rate and gives the maximum time in which to alter
these bits if necessary. Care should be taken when altering RT0 and
RT1 if the timeout period is imminent or uncertain. If the selected tap
is modified during a cycle in which the counter is switching, an RTIF
could be missed or an additional one could be generated. To avoid
problems, the COP should be cleared before changing RTI taps.
Table 10-1.
Table 10-2RTI and COP Rates at 2.048 MHz
RTI Rate
2.048 MHz
8 ms
2¹⁴/E
16 ms
2¹⁵/E
32 ms
2¹⁶/E
64 ms
2¹⁷/E
RT1
and RT0
00
01
10
11
Minimum COP Rates
2.048 MHz
(2¹⁷–2¹⁴)/E
56 ms
(2¹⁸–2¹⁵)/E
112 ms
(2¹⁹–2¹⁶)/E
224 ms
(2²⁰–2¹⁷)/E
448 ms
General Release Specification
MC68HC705CT4 — Rev. 2.0
82
Core Timer
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com