MC908GR8CDWE Datasheet, PDF (85/408 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Freescale Semiconductor, Inc.
Analog-to-Digital Converter (ADC)
I/O Registers
5.8 I/O Registers
These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADCLK)
5.8.1 ADC Status and Control Register
Function of the ADC status and control register (ADSCR) is described
here.
Address: $0003C
Bit 7
6
5
4
3
2
1
Bit 0
Read: _COCO/
Write: ^IDMAS
AIEN
ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Reset: 0
0
0
1
1
1
1
1
Figure 5-2. ADC Status and Control Register (ADSCR)
CAUTION:
COCO/IDMAS — Conversions Complete/Interrupt DMA Select Bit
When the AIEN bit is a logic 0, the COCO/IDMAS is a read-only bit
which is set each time a conversion is completed except in the
continuous conversion mode where it is set after the first conversion.
This bit is cleared whenever the ADSCR is written or whenever the
ADR is read.
If the AIEN bit is a logic 1, the COCO/IDMAS is a read/write bit which
selects either CPU or DMA to service the ADC interrupt request.
Reset clears this bit.
1 = Conversion completed (AIEN = 0)/DMA interrupt (AIEN = 1)
0 = Conversion not completed (AIEN = 0)/CPU interrupt (AIEN = 1)
Because the MC68HC908GR8 does NOT have a DMA module, the
IDMAS bit should NEVER be set when AIEN is set. Doing so will mask
ADC interrupts and cause unwanted results.
MC68HC908GR8 — Rev 4.0
MOTOROLA
Analog-to-Digital Converter (ADC)
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Technical Data
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