MC908GR8CDWE Datasheet, PDF (260/408 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Freescale Semiconductor, Inc.
Serial Communications Interface (SCI)
PEIE — Receiver Parity Error Interrupt Enable Bit
This read/write bit enables SCI receiver CPU interrupt requests
generated by the parity error bit, PE. See SCI Status Register 1.
Reset clears PEIE.
1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled
18.9.4 SCI Status Register 1
SCI status register 1 (SCS1) contains flags to signal these conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
• Parity error
Address: $0016
Bit 7
6
5
4
3
2
1
Bit 0
Read: SCTE
TC
SCRF IDLE
OR
NF
FE
PE
Write:
Reset: 1
1
0
0
0
0
0
0
= Unimplemented
Figure 18-12. SCI Status Register 1 (SCS1)
SCTE — SCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a
character to the transmit shift register. SCTE can generate an SCI
transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal
Technical Data
260
MC68HC908GR8 — Rev 4.0
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA