MC908GR8CDWE Datasheet, PDF (124/408 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGMC)
mode, such as when the PLL is first enabled and waiting for LOCK or
LOCK is lost.
7.8.2 Stop Mode
If the OSCSTOPENB bit in the CONFIG register is cleared (default),
then the STOP instruction disables the CGMC (oscillator and phase
locked loop) and holds low all CGMC outputs (CGMXCLK, CGMOUT,
and CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK,
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock,
CGMXCLK, divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.
If the OSCSTOPENB bit in the CONFIG register is set, then the phase
locked loop is shut off but the oscillator will continue to operate in stop
mode.
7.8.3 CGMC During Break Interrupts
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See SIM Break Flag Control
Register.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the PLLF bit during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
the PLL control register during the break state without affecting the PLLF
bit.
Technical Data
124
MC68HC908GR8 — Rev 4.0
Clock Generator Module (CGMC)
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