MC908GR8CDWE Datasheet, PDF (186/408 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
Addr. Register Name
Bit 7
6
5
4
3
2
Read: LVIOUT
0
0
0
0
0
$FE0C
LVI Status Register
(LVISR)
Write:
Reset: 0
0
0
0
0
0
= Unimplemented
Figure 14-2. LVI I/O Register Summary
1
Bit 0
0
0
0
0
14.4.1 Polled LVI Operation
In applications that can operate at V_DD levels below the V_TRIPF level,
software can monitor V_DD by polling the LVIOUT bit. In the configuration
register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
14.4.2 Forced Reset Operation
In applications that require V_DD to remain above the V_TRIPF level,
enabling LVI resets allows the LVI module to reset the MCU when V_DD
falls below the V_TRIPF level. In the configuration register, the LVIPWRD
and LVIRSTD bits must be at logic 0 to enable the LVI module and to
enable LVI resets.
14.4.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V_DD fall below V_TRIPF), the LVI
will maintain a reset condition until V_DD rises above the rising trip point
voltage, V_TRIPR. This prevents a condition in which the MCU is
continually entering and exiting reset if V_DD is approximately equal to
V_TRIPF. V_TRIPR is greater than V_TRIPF by the hysteresis voltage, V_HYS.
Technical Data
186
MC68HC908GR8 — Rev 4.0
Low-Voltage Inhibit (LVI)
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