MC908GR8CDWE Datasheet, PDF (70/408 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Freescale Semiconductor, Inc.
Resets and Interrupts
4.4.2 Sources
The sources in Table 4-1 can generate CPU interrupt requests.
Table 4-1. Interrupt Sources
Source
Flag
Mask⁽¹⁾
INT Register
Flag
Priority⁽²⁾
Vector
Address
Reset
None
None
None
0
$FFFE–$FFFF
SWI instruction
None
None
None
0
$FFFC–$FFFD
IRQ pin
IRQF
IMASK1
IF1
1
$FFFA–$FFFB
CGM (PLL)
PLLF
PLLIE
IF2
2
$FFF8–$FFF9
TIM1 channel 0
CH0F
CH0IE
IF3
3
$FFF6–$FFF7
TIM1 channel 1
CH1F
CH1IE
IF4
4
$FFF4–$FFF5
TIM1 overflow
TOF
TOIE
IF5
5
$FFF2–$FFF3
TIM2 channel 0
CH0F
CH0IE
IF6
6
$FFF0–$FFF1
TIM2 overflow
TOF
TOIE
IF8
8
$FFEC–$FFED
SPI receiver full
SPRF
SPRIE
SPI overflow
OVRF
ERRIE
IF9
9
$FFEA–$FFEB
SPI mode fault
MODF
ERRIE
SPI transmitter empty
SPTE
SPTIE
IF10
10
$FFE8–$FFE9
SCI receiver overrun
OR
ORIE
SCI noise fag
SCI framing error
NF
NEIE
IF11
FE
FEIE
11
$FFE6–$FFE7
SCI parity error
PE
PEIE
SCI receiver full
SCI input idle
SCRF
IDLE
SCRIE
ILIE
IF12
12
$FFE4–$FFE5
SCI transmitter empty
SCI transmission complete
SCTE
TC
SCTIE
TCIE
IF13
13
$FFE2–$FFE3
Keyboard pin
KEYF
IMASKK
IF14
14
$FFDE–$FFDF
ADC conversion complete
COCO
AIEN
IF15
15
$FFDE–$FFDF
Timebase
TBIF
TBIE
IF16
16
$FFDC–$FFDD
Note:
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction.
2. 0 = highest priority
Technical Data
70
MC68HC908GR8 — Rev 4.0
Resets and Interrupts
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