MC908GR8CDWE Datasheet, PDF (42/408 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Memory Map
Freescale Semiconductor, Inc.
Addr. Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Configuration Register 2 ^{Read: 0}
0
0
0
0
0
OSC- SCIBD-
$001E
(CONFIG2)† Write:
STOPENB SRC
Reset: 0
0
0
0
0
0
0
0
$001F
Read:
Configuration Register 1
(CONFIG1)^†
Write:
Reset:
COPRS
0
LVISTOP LVIRSTD LVIPWRD LVI5OR3^†
0
0
0
0
SSREC
0
STOP
0
COPD
0
Read: TOF
0
0
$0020
Timer 1 Status and Control
Register (T1SC)
Write:
0
TOIE TSTOP
TRST
Reset: 0
0
1
0
0
PS2
PS1
PS0
0
0
0
Read: Bit 15
14
13
12
11
10
$0021
Timer 1 Counter Register
High (T1CNTH)
Write:
Reset: 0
0
0
0
0
0
9
Bit 8
0
0
Read: Bit 7
6
5
4
3
2
1
Bit 0
$0022
Timer 1 Counter Register
Low (T1CNTL)
Write:
Reset: 0
0
0
0
0
0
0
0
Read:
$0023
Timer 1 Counter Modulo
Register High (T1MODH)
Write:
Bit 15
14
13
12
11
10
Reset: 1
1
1
1
1
1
9
Bit 8
1
1
Read:
$0024
Timer 1 Counter Modulo
Register Low (T1MODL)
Write:
Bit 7
6
5
4
3
2
1
Bit 0
Reset: 1
1
1
1
1
1
1
1
Timer 1 Channel 0 Status ^Read:
$0025 and Control Register Write:
(T1SC0) _Reset:
CH0F
0
0
CH0IE
0
MS0B
0
MS0A
0
ELS0B ELS0A
0
0
TOV0 CH0MAX
0
0
Read:
$0026
Timer 1 Channel 0
Register High (T1CH0H)
Write:
Bit 15
14
Reset:
13
12
11
10
Indeterminate after reset
9
Bit 8
Read:
$0027
Timer 1 Channel 0
Register Low (T1CH0L)
Write:
Bit 7
6
Reset:
5
4
3
2
Indeterminate after reset
1
Bit 0
† One-time writeable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).
= Unimplemented R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)
Technical Data
42
MC68HC908GR8 — Rev 4.0
Memory Map
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