MC908GR8CDWE Datasheet, PDF (210/408 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Freescale Semiconductor, Inc.
Input/Output Ports (I/O)
16.3.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is
an input or an output. Writing a logic 1 to a DDRA bit enables the output
buffer for the corresponding port A pin; a logic 0 disables the output
buffer.
Address: $0004
Bit 7
6
5
4
3
2
1
Read: 0
0
0
0
DDRA3 DDRA2 DDRA1
Write:
Reset: 0
0
0
0
0
0
0
Figure 16-3. Data Direction Register A (DDRA)
Bit 0
DDRA0
0
DDRA3–DDRA0 — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA3–DDRA0, configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 16-4 shows the port A I/O logic.
Technical Data
210
MC68HC908GR8 — Rev 4.0
Input/Output Ports (I/O)
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