MC908GR8CDWE Datasheet, PDF (106/408 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGMC)
• Software must wait a given time, t_AL, after entering tracking mode
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGMC are disabled.
7.4.6 Programming the PLL
The following procedure shows how to program the PLL.
NOTE: The round function in the following equations means that the real
number should be rounded to the nearest integer number.
1. Choose the desired bus frequency, f_BUSDES.
2. Calculate the desired VCO frequency (four times the desired bus
frequency).
f_VCLKDES = 4 × f_BUSDES
3. Choose a practical PLL (crystal) reference frequency, f_RCLK, and
the reference clock divider, R. Typically, the reference crystal is
32.768 kHz and R = 1.
Frequency errors to the PLL are corrected at a rate of f_RCLK/R. For
stability and lock time reduction, this rate must be as fast as
possible. The VCO frequency must be an integer multiple of this
rate. The relationship between the VCO frequency, f_VCLK, and the
reference frequency, f_RCLK, is
f_VCLK = ^2----P_R----N---(f_RCLK)
P, the power of two multiplier, and N, the range multiplier, are
integers.
In cases where desired bus frequency has some tolerance,
choose f_RCLK to a value determined either by other module
requirements (such as modules which are clocked by CGMXCLK),
cost requirements, or ideally, as high as the specified range
Technical Data
106
MC68HC908GR8 — Rev 4.0
Clock Generator Module (CGMC)
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