MC908GR8CDWE Datasheet, PDF (120/408 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGMC)
NOTE: The multiplier select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1).
PMSH[7:4] — Unimplemented Bits
These bits have no function and always read as logic 0s.
7.6.4 PLL Multiplier Select Register Low
The PLL multiplier select register low (PMSL) contains the programming
information for the low byte of the modulo feedback divider.
Address: $0038
Bit 7
6
5
4
3
2
1
Bit 0
Read:
MUL7
Write:
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
MUL0
Reset: 0
1
0
0
0
0
0
0
Figure 7-7. PLL Multiplier Select Register Low (PMSL)
MUL7–MUL0 — Multiplier Select Bits
These read/write bits control the low byte of the modulo feedback
divider that selects the VCO frequency multiplier, N. (See PLL Circuits
and Programming the PLL.) MUL7–MUL0 cannot be written when the
PLLON bit in the PCTL is set. A value of $0000 in the multiplier select
registers configures the modulo feedback divider the same as a value
of $0001. Reset initializes the register to $40 for a default multiply
value of 64.
NOTE: The multiplier select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1).
Technical Data
120
MC68HC908GR8 — Rev 4.0
Clock Generator Module (CGMC)
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