MC908GR8CDWE Datasheet, PDF (187/408 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
LVI Status Register
14.4.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is
configured for 5V or 3V protection.
NOTE:
The microcontroller is guaranteed to operate at a minimum supply
voltage. The trip point (V_TRIPF [5 V] or V_TRIPF [3 V]) may be lower than
this. (See Electrical Specifications for the actual trip point voltages.)
14.5 LVI Status Register
The LVI status register (LVISR) indicates if the V_DD voltage was
detected below the V_TRIPF level.
Address: $FE0C
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-3. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the
V_TRIPF trip voltage. See Table 14-1. Reset clears the LVIOUT bit.
Table 14-1. LVIOUT Bit Indication
V_DD
V_DD > V_TRIPR
V_DD < V_TRIPF
V_TRIPF < V_DD < V_TRIPR
LVIOUT
0
1
Previous value
MC68HC908GR8 — Rev 4.0
MOTOROLA
Low-Voltage Inhibit (LVI)
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Technical Data
187