MC908GR8CDWE Datasheet, PDF (115/408 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGMC)
CGMC Registers
$003A
Read:
PLL VCO Select Range
Register (PMRS)
Write:
Reset:
VRS7
0
VRS6
1
VRS5
0
VRS4
0
VRS3
0
VRS2
0
Read: 0
0
0
0
$003B
PLL Reference Divider
Select Register (PMDS)
Write:
RDS3 RDS2
Reset: 0
0
0
0
0
0
= Unimplemented
R = Reserved
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 7-3. CGMC I/O Register Summary
VRS1
0
RDS1
0
VRS0
0
RDS0
1
7.6.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag
bits, the on/off switch, the base clock selector bit, the prescaler bits, and
the VCO power-of-two range selector bits.
Address: $0036
Bit 7
6
5
4
3
2
1
Read:
PLLIE
Write:
PLLF
PLLON BCS
PRE1 PRE0 VPR1
Reset: 0
0
1
0
0
0
0
= Unimplemented
Figure 7-4. PLL Control Register (PCTL)
Bit 0
VPR0
0
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
MC68HC908GR8 — Rev 4.0
MOTOROLA
Clock Generator Module (CGMC)
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Technical Data
115