MC908GR8CDWE Datasheet, PDF (170/408 Pages) Freescale Semiconductor, Inc – M68HC08 Microcontrollers

Freescale Semiconductor, Inc.
External Interrupt (IRQ)
12.5 IRQ1 Pin
A logic 0 on the IRQ1 pin can latch an interrupt request into the IRQ
latch. A vector fetch, software clear, or reset clears the IRQ latch.
If the MODE bit is set, the IRQ1 pin is both falling-edge-sensitive and
low-level-sensitive. With MODE set, both of the following actions must
occur to clear IRQ:
• Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK bit in the interrupt status and control register (INTSCR).
The ACK bit is useful in applications that poll the IRQ1 pin and
require software to clear the IRQ latch. Writing to the ACK bit prior
to leaving an interrupt service routine can also prevent spurious
interrupts due to noise. Setting ACK does not affect subsequent
transitions on the IRQ1 pin. A falling edge that occurs after writing
to the ACK bit another interrupt request. If the IRQ mask bit,
IMASK, is clear, the CPU loads the program counter with the
vector address at locations $FFFA and $FFFB.
• Return of the IRQ1 pin to logic 1 — As long as the IRQ1 pin is at
logic 0, IRQ remains active.
The vector fetch or software clear and the return of the IRQ1 pin to logic
1 may occur in any order. The interrupt request remains pending as long
as the IRQ1 pin is at logic 0. A reset will clear the latch and the MODE
control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ1 pin is falling-edge-sensitive only. With
MODE clear, a vector fetch or software clear immediately clears the IRQ
latch.
Technical Data
170
MC68HC908GR8 — Rev 4.0
External Interrupt (IRQ)
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