M0564LE4AE Datasheet, PDF (93/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

M0564
6.9 General Purpose I/O (GPIO)
6.9.1 Overview
The M0564 series has up to 86 General Purpose I/O pins to be shared with other function pins
depending on the chip configuration. These 86 pins are arranged in 6 ports named as PA, PB,
PC, PD, PE and PF. PA, PB, PC, PD has 16 pins on port. PE has 14 pins on port. PF has 8 pins
on port. Each of the 86 pins is independent and has the corresponding register bits to control the
pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull
output, Open-drain output or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all
pins are depending on CIOIN (CONFIG0[10]). Each I/O pin has a very weakly individual pull-up
resistor which is about 110 k ~ 300 k for V_DD is from 5.0 V to 2.5 V.
6.9.2
Features
 Four I/O modes:
– Quasi-bidirectional mode
– Push-Pull Output mode
– Open-Drain Output mode
– Input only with high impendence mode
 TTL/Schmitt trigger input selectable
 I/O pin can be configured as interrupt source with edge/level setting
 Supports High Slew Rate I/O mode
 Configurable default I/O mode of all pins after reset by CIOINI (CONFIG0[10]) setting
– CIOIN = 0, all GPIO pins in input tri-state mode after chip reset
– CIOIN = 1, all GPIO pins in Quasi-bidirectional mode after chip reset
 I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
 Enabling the pin interrupt function will also enable the wake-up function
May 05, 2017
Page 93 of 161
Rev 1.00