M0564LE4AE Datasheet, PDF (123/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

M0564
6.17.3.18 Polarity Control
Each PWMx_CH0 and PWMx_CH1 has an independent polarity control to configure the polarity
of the active state of PWM output. User can control polarity state of PWMx_CH0 on PINV0
(TIMERx_PWMPOLCTL[0]) and PWMx_CH1 on PINV1 (TIMERx_PWMPOLCTL[1]). Figure
6.17-22 shows the PWMx_CH0 and PWMx_CH1 output with polarity control and dead-time
insertion.
Initial State PWM Starts
PWMx_CH0
PWMx_CH1
PWMx_CH0
PWMx_CH1
(PINV0=0)
(PINV1=0)
PWMx_CH0
PWMx_CH1
(PINV0=1)
(PINV1=0)
PWMx_CH0
PWMx_CH1
(PINV0=0)
(PINV1=1)
PWMx_CH0
PWMx_CH1
(PINV0=1)
(PINV1=1)
Note1: dead-time insertion
Note2: PINV0/PIV1, it controls the output polar inverse
Figure 6.17-22 PWMx_CH0 and PWMx_CH1 Polarity Control with Dead-Time Insertion
6.17.3.19 PWM Interrupt Generator
There are independent interrupts for each PWM as shown in Figure 6.17-23.
The PWM interrupt (PWMx_INT) comes from PWM complementary pair events. The counter can
generate the zero point interrupt flag ZIF (TIMERx_PWMINTSTS0[0]) and the period point
interrupt flag PIF (TIMERx_PWMINTSTS0[1]). When counter equals to the comparator value
stored in CMP (TIMERx_PWMCMPDAT[15:0]), the different interrupt flags will be triggered
depending on the counting direction. If counter and CMP matched occurs at up-count direction,
the comparator up interrupt flag CMPUIF (TIMERx_PWMINTSTS0[2]) is set and if matched at
down-count direction, the comparator down interrupt flag CMPDIF (TIMERx_PWMINTSTS0[3]) is
set. If the corresponding interrupt enable bits are set, the interrupt trigger events will also
generates interrupt signals. When PWM brake event occurred, the relatives interrupt event will be
triggered according to PWM brake settings.
May 05, 2017
Page 123 of 161
Rev 1.00