M0564LE4AE Datasheet, PDF (83/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

M0564
48 MHz
22.1184
MHz
4~24
MHz
32.768
kHz
10 kHz
4488 MMHHzz
2222..11118844 MMHHzz
110000
111111
1100 kkHHzz
PPLLLLFFOOUUTT
001111
001100
3322..776688 kkHHzz
44~~2244 MMHHzz
000011
000000
CLK_CLKSEL0[2:0]
2222..11118844 MMHHzz
11
44~~2244 MMHHzz
00
PLL FOUT
CCLLKK__PPLLLLCCTTLL[[1199]]
1100 kkHHzz
2222..11118844 MMHHzz
BOD
FMC
CPUCLK
1/(HCLKDIV+
1)
HCLK
CLK_CLKSEL
0[6]
1/2 11
00
PCLK
0
1/2 11
00
CLK_CLKSEL
0[7]
PCLK
1
2222..11118844 MMHHzz
1100 kkHHzz
111111
110011
TT00~~TT33
PPCCLLKK
001111
001100
3322..776688 kkHHzz
44~~2244 MMHHzz
000011
000000
CPU
CRC
PDMA
EBI
HDIV
USCI1
I2C1
I2C0
ACMP
USCI0/2
TMR 0
TMR 1
TMR 2
TMR 3
CLK_CLKSEL1 [10:8]
CLK_CLKSEL1[14:12]
CLK_CLKSEL1[18:16]
CLK_CLKSEL1[22:20]
1100 kkHHzz
11
3322..776688kkHHzz ₀₀
CLK_CLKSEL2[
18]
4488 MMHHzz
110011
2222..11118844 MMHHzz
HHCCLLKK
3322..776688 kkHHzz
001111
001100
000011
44~~2244MMHHzz ₀₀₀₀₀₀
CLK_CLKSEL2[4:
2]
4488 MMHHzz
PPCCLLKK
1111
1100
PPLLLLFFOOUUTT
0011
44~~2244MMHHzz 0000
RTC
Clock Output
SPI0
SPI1
CLK_CLKSEL2[25:24]
CLK_CLKSEL2[27:26]
2222..11118844 MMHHzz
PPCCLLKK
1111
1100
PPLLLLFFOOUUTT
0011
44~~2244MMHHzz ₀₀₀₀
CLK_CLKSEL1[3:2]
1/(ADCDIV)+1
ADC
2222..11118844 MMHHzz
PPCCLLKK
1111
1100
PPLLLLFFOOUUTT
0011
44~~2244MMHHzz ₀₀₀₀
CLK_CLKSEL3[1:0]
CLK_CLKSEL3[3:2]
2222..11118844MMHHzz _1/2
111111
HHCCLLKK
1/2
001111
44~~2244 MMHHzz
1/2
001100
3322..776688 kkHHzz
000011
44~~2244 MMHHzz
000000
CLK_CLKSEL0[5:3]
CCPPUUCCLLKK
11
00
SSYYSSTT__CCSSRR
SysTick
PPCCLLKK
11
PPLLLLFFOOUUTT ₀₀
CLK_CLKSEL1[28]
CLK_CLKSEL1[29]
1100
kkHHzz
1111
HHCCLLKK
1/2048
1100
3322..776688kkHHzz ₀₀₁₁
CCLLKK__CCLLKKSSEELL11[[11::00]]
PWM 0
PWM 1
WDT
1100 kkHHzz
1111
HHCCLLKK
1/2048
1100
CCLLKK__CCLLKKSSEELL11[[3311::3300]]
SMC0
SMC1
3322..776688 KKHHzz
2222..11118844 MMHHzz
1100
1111
PPLLLLFFOOUUTT
44~~2244 MMHHzz
0011
0000
CLK_CLKSEL1[25:24]
WWDT
1/(UARTDIV+1)
UART 0-2
Note: Before clock switching, both the pre-selected and newly selected clock source must be turned on and stable.
Figure 6.3-2 Clock Generator Global View Diagram
May 05, 2017
Page 83 of 161
Rev 1.00