M0564LE4AE Datasheet, PDF (110/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

M0564
CNT
(TIMERx_PWMCNT[15:0])
DIRF
(TIMERx_PWMCNT[16])
CNTEN
(TIMERx_PWMCTL[0])
zero point event
center point event
PERIOD = 4
PERIOD = 7
012343210123456765432101234
PWM Period
PWM Period
Note: When in up-down count type, period interrupt flag occurs at center point event.
Figure 6.17-4 PWM Up-Down Count Type
6.17.3.6 PWM Counter Operation mode
The PWM counter supports two operation modes: one-shot mode and auto-reload mode. PWM
counter will operate in one-shot mode if CNTMODE (TIMERx_PWMCTL[3]) bit is set to 1, and
operate in auto-reload mode if CNTMODE bit is set to 0.
In
both
modes,
CMP
(TIMERx_PWMCMPDAT[15:0])
and
PERIOD
(TIMERx_PWMPERIOD[15:0]) should be written first and then set CNTEN
(TIMERx_PWMCTL[0]) bit to 1 to start counter running.
In one-shot mode, PWM counter value will reload to default value according count type after one
PWM period is completed. User can write CMP to continuous one-shot operation to generate next
one-shot pulse once no matter current one-shot counter is running or completed.
In auto-reload mode, PWM counter is continuous running with current active PERIOD and CMP. If
user set PERIOD to zero in auto-reload mode, PWM counter value will reload to default value
according count type after one PWM period is completed.
6.17.3.7 PWM Comparator
The CMP (TIMERx_PWMCMPDAT[15:0]) is comparator register of PWM. The CMP value is
continuously compared to the corresponding counter value. When the counter is equal to CMP,
PWM generates a compared point event. This event will generate PWM output pulse, interrupt
signal or trigger ADC start convert. In up-down count type, two events will be generated in a PWM
period as shown in Figure 6.17-5. The CMPU is up count compared point event and CMPD is
down count compared point event.
May 05, 2017
Page 110 of 161
Rev 1.00