M0564LE4AE Datasheet, PDF (120/161 Pages) List of Unclassifed Manufacturers – 32-BIT MICROCONTROLLER

M0564
CNT
(TIMERx_PWMCNT[15:0])
Edge Detect
Brake Source
BRKEIF0
(TIMERx_PWMINTSTS1[0])
BRKEIF1
(TIMERx_PWMINTSTS1[1])
BRKESTS0
(TIMERx_PWMINTSTS1[16])
BRKESTS1
TIMERx_PWMINTSTS1[17])
PWMx_CH0
PWMx_CH1
s/w clear
s/w clear
PWMx_CH0 resume at next start of
PWM period after BRKEIF0 is cleared
Note1: BRKACT0: 0x11, output high at brake condition
BRKACT1: 0x10, output low at brake condition
Note2: Output Brake State
PWMx_CH1 resume at next start of
PWM period after BRKEIF1 is cleared
Figure 6.17-18 Edge Detector Brake Waveform for PWMx_CH0 and PWMx_CH1
When the level detector detects the brake signal, the brake function generates interrupt status for
PWMx_CH1/0 is BRKLIF1/0 (TIMERx_PWMINTSTS1[9:8]) and brake event status for
PWMx_CH1/0 is BRKLSTS1/0 (TIMERx_PWMINTSTS1[25:24]). The interrupt status BRKLIF1/0
can be cleared by writing 1 to it, and the brake event status BRKLSTS1/0 will be cleared only
when current period is completed and brake condition removed, then PWM generator can resume
normal output when next PWM period starts.
Figure 6.17-19 shows an example of level detector brake waveform for PWMx_CH0 and
PWMx_CH1. In this case, the BRKLIF0 and BRKLIF1 can only indicate the brake event has
occurred, writes 1 to clear this flags will not affect BRKLSTS0 and BRKLSTS1 brake event status.
Both BRKLSTS0 and BRKLSTS1 brake states will automatically cleared at the start of the next
PWM period when level brake condition has released no matter BRKLIF0 and BRKLIF1 status.
May 05, 2017
Page 120 of 161
Rev 1.00